Due to the growing complexity of modern Integrated Circuits (ICs), there is a need for automated circuit design methods. Recent years have seen rising research in hardware design language generation to facilitate the design process. In this work, we propose a Verilog generation framework, BetterV, which fine-tunes the large language models (LLMs) on processed domain-specific datasets and incorporates generative discriminators for guidance on particular design demands. The Verilog modules are collected, filtered and processed from internet to form a clean and abundant dataset. Instruct-tuning methods are specially designed to fine-tuned the LLMs to understand the knowledge about Verilog. Furthermore, data are augmented to enrich the training set and also used to train a generative discriminator on particular downstream task, which leads a guidance for the LLMs to optimize the Verilog implementation. BetterV has the ability to generate syntactically and functionally correct Verilog, which can outperform GPT-4 on the VerilogEval-machine benchmark. With the help of task-specific generative discriminator, BetterV can achieve remarkable improvement on various electronic design automation (EDA) downstream tasks, including the netlist node reduction for synthesis and verification runtime reduction with Boolean Satisfiability (SAT) solving.

翻译：由于现代集成电路（IC）日益增长的复杂性，亟需自动化电路设计方法。近年来，硬件描述语言生成方面的研究不断兴起，旨在促进设计流程。本文提出了一种Verilog生成框架BetterV，该框架对处理后的领域特定数据集上的大型语言模型（LLM）进行微调，并集成生成性判别器以引导特定设计需求。我们从互联网收集、过滤并处理Verilog模块，构建了一个干净且丰富的数据集。特别设计了指令微调方法，使大型语言模型能够理解Verilog相关知识。此外，通过数据增强丰富训练集，并利用这些数据在特定下游任务上训练生成性判别器，从而引导大型语言模型优化Verilog实现。BetterV能够生成语法正确且功能正确的Verilog代码，在VerilogEval-machine基准测试上可超越GPT-4。借助任务特定的生成性判别器，BetterV能在各种电子设计自动化（EDA）下游任务上取得显著改进，包括通过布尔可满足性（SAT）求解实现综合阶段的网表节点缩减以及验证运行时间的减少。