Achieving high performance, energy efficiency, and cost-effectiveness while maintaining architectural flexibility is a critical challenge in the development and deployment of edge AI devices. Monolithic SoC designs struggle with this complex balance mainly due to low manufacturing yields (below 16%) at advanced 360 mm^2 process nodes. This paper presents a novel chiplet-based RISC-V SoC architecture that addresses these limitations through modular AI acceleration and intelligent system level optimization. Our proposed design integrates 4 different key innovations in a 30mm x 30mm silicon interposer: adaptive cross-chiplet Dynamic Voltage and Frequency Scaling (DVFS); AI-aware Universal Chiplet Interconnect Express (UCIe) protocol extensions featuring streaming flow control units and compression-aware transfers; distributed cryptographic security across heterogeneous chiplets; and intelligent sensor-driven load migration. The proposed architecture integrates a 7nm RISC-V CPU chiplet with dual 5nm AI accelerators (15 TOPS INT8 each), 16GB HBM3 memory stacks, and dedicated power management controllers. Experimental results across industry standard benchmarks like MobileNetV2, ResNet-50 and real-time video processing demonstrate significant performance improvements. The AI-optimized configuration achieves ~14.7% latency reduction, 17.3% throughput improvement, and 16.2% power reduction compared to previous basic chiplet implementations. These improvements collectively translate to a 40.1% efficiency gain corresponding to ~3.5 mJ per MobileNetV2 inference (860 mW/244 images/s), while maintaining sub-5ms real-time capability across all experimented workloads. These performance upgrades demonstrate that modular chiplet designs can achieve near-monolithic computational density while enabling cost efficiency, scalability and upgradeability, crucial for next-generation edge AI device applications.

翻译：在边缘AI设备的开发与部署中，实现高性能、高能效与成本效益的平衡同时保持架构灵活性是一项关键挑战。传统单片SoC设计难以实现这一复杂平衡，主要原因是先进360 mm²工艺节点的制造良率较低（低于16%）。本文提出了一种新型基于芯粒的RISC-V SoC架构，通过模块化AI加速与智能系统级优化来克服这些限制。我们的设计方案在30mm×30mm硅中介层上集成了4项关键创新：跨芯粒自适应动态电压频率缩放（DVFS）、具备流控单元与压缩感知传输特性的AI感知通用芯粒互连协议（UCIe）扩展、异构芯粒间的分布式加密安全机制，以及智能传感器驱动的负载迁移。该架构集成了7nm RISC-V CPU芯粒、双5nm AI加速器（各15 TOPS INT8）、16GB HBM3内存堆叠以及专用电源管理控制器。基于MobileNetV2、ResNet-50等工业标准基准测试及实时视频处理的实验结果表明，性能显著提升。与先前基础芯粒实现相比，AI优化配置实现了约14.7%的延迟降低、17.3%的吞吐量提升和16.2%的功耗降低。这些改进综合带来了40.1%的效率增益，对应MobileNetV2推理约3.5 mJ（860 mW/244 images/s），同时所有实验负载均保持亚5ms实时处理能力。这些性能提升表明，模块化芯粒设计能够在实现近单片计算密度的同时，提供成本效益、可扩展性与可升级性，这对下一代边缘AI设备应用至关重要。