While functional RISC-V implementations are readily available in academia, controlled empirical studies that extend a single baseline architecture along multiple design axes and quantify the resulting trade-offs at each step remain scarce. This paper presents RV-IM100, a family of 10 incremental FPGA-implemented microarchitectures derived from a common 5-stage pipeline baseline, systematically varying datapath width from RV32 to RV64, instruction set from I to IM, and pipeline depth from 5 to 8~stages under controlled conditions. Using an iterative timing-closure methodology, RV32IM frequency improved from 43 to 126MHz, increasing Dhrystone throughput by 64% and CoreMark by 300%, while per-MHz efficiency decreased by 36--41%. The 6-to-7-stage transition caused throughput regression in RV64 despite higher frequency, revealing that the outcome depends on available frequency headroom. Cross-width comparison showed RV32 outperforming RV64 in absolute throughput, with per-MHz efficiency diverging by benchmark: RV64 led by 2.3% in DMIPS/MHz while RV32 led by 4.6% in CoreMark/MHz. At 8 stages, RV32 required 59% fewer LUTs, 51% fewer FFs, and 80% fewer DSPs, indicating that the resource cost of width extension substantially exceeds the modest efficiency differences. These results provide a quantitative reference for design-space exploration in RISC-V microarchitectures. All RTL sources and benchmark configurations are publicly available.

翻译：尽管学术界已可获得功能完备的RISC-V实现，但针对单一基线架构沿多个设计维度扩展并量化各阶段权衡的受控实证研究仍较罕见。本文提出RV-IM100微架构家族——基于公共5级流水线基线的10个增量式FPGA实现，在受控条件下系统化调整数据通路宽度（RV32至RV64）、指令集（I至IM）及流水线深度（5至8级）。通过迭代时序收敛方法，RV32IM工作频率从43MHz提升至126MHz，Dhrystone吞吐量增加64%、CoreMark增加300%，但每MHz效率下降36%-41%。在6级向7级流水线过渡时，尽管RV64频率提升，吞吐量却出现倒退，表明结果取决于可用频率余量。跨宽度对比显示：绝对吞吐量方面RV32优于RV64，而每MHz效率因基准测试而异——DMIPS/MHz指标下RV64领先2.3%，CoreMark/MHz指标下RV32领先4.6%。在8级流水线配置中，RV32所需LUT减少59%、FF减少51%、DSP减少80%，表明宽度扩展的资源成本远超其微小的效率差异。这些结果为RISC-V微架构的设计空间探索提供了量化参考。所有RTL源码与基准测试配置均已公开。