Time-sensitive networking (TSN) is a set of IEEE standards that extends Ethernet with real-time capabilities. Among its mechanisms, the time-aware shaper (TAS) periodically opens and closes egress queues to protect scheduled traffic from lower-priority flows, ensuring low latency and bounded delay. Deterministic networking (DetNet), standardized by the IETF, provides similar guarantees at Layer 3 and can leverage TSN mechanisms such as the TAS. Commercially available TSN-capable switches implement TAS in hardware but rarely disclose internal delays in the TAS mechanism itself. Such delays directly affect scheduling precision, yet information about them is largely unavailable to system designers. In this work, we present P4-TAS, a P4-based implementation of the TAS on the Intel Tofino 2 switching ASIC that additionally supports per-stream filtering and policing (PSFP) and PTP time synchronization. First, we design a novel mechanism for periodic queue control that uses a continuous stream of internally generated control frames for time-triggered queue state updates. To the best of our knowledge, this enables TAS on a P4-programmable ASIC for the first time. P4-TAS additionally provides an MPLS/TSN translation layer that enables TSN time-based shaping to be applied at the boundary between TSN and DetNet domains, supporting line rates up to 400 Gb/s per port. Second, we identify and quantify three sources of internal delay that affect the precision of TAS gate transitions, providing transparency that enables more accurate TAS configuration. Our evaluation demonstrates a worst-case accumulated internal delay of 86 ns between time slices, which is well below values reported for commercial switches. Third, we propose a measurement methodology to externally measure TAS time slice accuracy, and introduce gate switching intervals (GSIs) to mitigate overlap between consecutive time slices.

翻译：时间敏感网络（TSN）是一组IEEE标准，通过实时能力扩展以太网。其中，时间感知整形器（TAS）周期性地打开和关闭出口队列，以保护计划流量免受低优先级流的影响，从而确保低延迟和有界延迟。IETF标准化的确定性网络（DetNet）在第三层提供类似的保障，并可利用TSN机制（如TAS）。商用的TSN交换机在硬件中实现TAS，但很少公开TAS机制本身的内部延迟。此类延迟直接影响调度精度，但系统设计者几乎无法获得相关信息。本文提出P4-TAS，一种基于P4的TAS实现，运行于Intel Tofino 2交换ASIC上，额外支持每流过滤与监管（PSFP）及PTP时间同步。首先，我们设计了一种新型周期队列控制机制，利用连续生成的内部控制帧进行时间触发的队列状态更新。据我们所知，这首次在P4可编程ASIC上实现了TAS。P4-TAS还提供了MPLS/TSN转换层，使得TSN基于时间的整形能够在TSN与DetNet域边界应用，支持每端口高达400 Gb/s的线速。其次，我们识别并量化了影响TAS门控转换精度的三种内部延迟源，提供了透明度，从而实现更精确的TAS配置。评估表明，时间片之间的最坏累积内部延迟为86 ns，远低于商用交换机报告的值。最后，我们提出了一种测量方法，用于外部测量TAS时间片精度，并引入门控切换间隔（GSI）以减轻连续时间片之间的重叠。