Pre-implementation behavioural simulation routinely validates functional correctness, yet it also produces rich switching-activity traces that are typically discarded by FPGA computer-aided design (CAD) flows. Prior simulation-guided and power-aware FPGA optimisations demonstrate the promise of exploiting this metadata, but many rely on fixed thresholds, narrow decision heuristics, or limited design awareness, often incurring substantial area overhead. This paper presents Context-aware Simopt-Power, a simulator-guided optimisation framework that combines activity metadata with lightweight structural features (sequential proximity, logic-depth proxies, and fan-out estimates) to more precisely target high-impact regions of the netlist. We additionally remove empirically tuned constants, replacing them with architecture-aware parameters such as LUT size and mapping constraints, and evaluate trade-offs using power, delay, and a more useful metrics, area-delay product (AD) and power-delay product (PD). Implemented in an open-source Yosys/ABC flow and evaluated on the complex Koios deep-learning accelerator benchmarks, Context-aware Simopt-Power achieves an average 6.8% dynamic-power reduction while limiting LUT overhead to 11.2%, thus enabling a holistic design optimisation.

翻译：预实现行为仿真通常用于验证功能正确性，但其产生的丰富开关活动轨迹常被FPGA计算机辅助设计（CAD）流程丢弃。先前的仿真引导与功耗感知FPGA优化方法展示了利用此类元数据的潜力，但许多方法依赖固定阈值、狭窄决策启发式或有限的设计感知能力，往往导致显著的面积开销。本文提出上下文感知Simopt-Power——一种仿真引导的优化框架，将活动元数据与轻量级结构特征（时序邻近性、逻辑深度代理及扇出估计）相结合，以更精准地定位网表中的高影响区域。此外，我们移除了经验调优常数，代之以架构感知参数（如查找表（LUT）大小与映射约束），并通过功耗、延迟以及更有用的度量标准——面积延迟积（AD）与功耗延迟积（PD）来评估权衡。该框架在开源Yosys/ABC流程中实现，并在复杂的Koios深度学习加速器基准上评估，实现了平均6.8%的动态功耗降低，同时将LUT开销限制在11.2%，从而实现整体设计优化。