Modern multicore system-on-chips (SoCs) share off-chip DRAM across cores, where bank-level interference can significantly degrade performance and threaten real-time guarantees. While prior work has focused on per-core bandwidth regulation, these approaches treat main memory as a monolithic resource and overlook DRAM's inherent bank-level parallelism. We show that DRAM interference is fundamentally a bank-level phenomenon. We characterize the guaranteed bandwidth of modern DRAM, demonstrate that it remains effectively constant across generations, and show how this limitation can be exploited by single-bank attacks. These results highlight the need for bank-aware memory management for predictable and efficient real-time systems. We design and implement a novel per-bank memory bandwidth regulator in an open-source RISC-V SoC and evaluate it using FireSim with both synthetic and real-world workloads. Our evaluation demonstrates that per-bank regulation effectively mitigates adversarial bank contention and achieves a 5.74x average throughput improvement for best-effort workloads over traditional bank-oblivious approaches while providing the same-level of performance isolation guarantees for real-time workloads.

翻译：现代多核片上系统在多核之间共享片外DRAM，其中存储体级干扰会显著降低性能并威胁实时性保障。现有工作主要关注逐核带宽调控，但这些方法将主存视为单一资源，忽视了DRAM固有的存储体级并行性。我们论证了DRAM干扰本质上是存储体级现象。通过刻画现代DRAM的保证带宽特性，我们发现该带宽在各代际间保持恒定有效，并展示了单存储体攻击如何利用这一局限。这些结果凸显了为构建可预测且高效的实时系统而需要采用存储体感知内存管理的必要性。我们在开源RISC-V SoC上设计并实现了一种新型逐存储体内存带宽调节器，通过FireSim在合成负载与真实工作负载下进行评测。实验表明，相较于传统无视存储体的方法，逐存储体调控能有效缓解对抗性存储体竞争，在为实时工作负载提供同等性能隔离保证的同时，将尽力而为工作流的平均吞吐量提升5.74倍。