High-level synthesis (HLS) performs well for simple memory access patterns, such as for sequential accesses that can be turned into bursts, or for memory accesses into small datasets that can be stored in scratchpads. This limits HLS to accelerating only the low-hanging fruit, where memory-level parallelism is either trivially abundant, due to simple access patterns, or latency is low, due to the small dataset. Applications with more complex access patterns on large datasets would also benefit from acceleration, and would especially benefit from the reduction in design and verification effort that HLS promises. In this paper, we present DAE4HLS, a decoupled access-execute (DAE) paradigm for HLS. We propose a new programming model for explicitly decoupling requests and responses, which unlocks memory-level parallelism that otherwise cannot be automatically provided by a compiler. We apply the DAE4HLS paradigm to the commercial AMD Vitis HLS toolchain and show that the existing AXI stream and AXI burst interfaces can be repurposed for explicit decoupling. We further apply the paradigm to a dynamic-HLS framework, which is better suited for handling irregular workloads as compared to statically scheduled HLS. We show that support for explicit decoupling improves the performance and achieves a total speedup of 10-79$\times$.

翻译：高层次综合（HLS）在简单存储器访问模式下表现良好，例如可转化为突发传输的顺序访问，或可存储在便签存储器中的小数据集访问。这限制HLS仅能加速“低垂果实”，即访存模式简单而存储器级并行性充分，或数据集小而导致延迟低。对于大数据集上具有更复杂访存模式的应用，加速同样受益，尤其是HLS所承诺的设计与验证工作量的减少。本文提出DAE4HLS，一种面向HLS的解耦访问-执行（DAE）范式。我们提出了一种新的显式解耦请求与响应的编程模型，该模型释放了编译器无法自动提供的存储器级并行性。我们将DAE4HLS范式应用于商业AMD Vitis HLS工具链，并证明现有的AXI流与AXI突发接口可被重新用于显式解耦。进一步，我们将该范式应用于动态HLS框架，该框架相较于静态调度HLS更适合处理不规则工作负载。结果表明，支持显式解耦提升了性能，实现了10-79倍的总加速比。