We propose using Vision-Language Models (VLMs) for macro placement in chip floorplanning, a complex optimization task that has recently shown promising advancements through machine learning methods. Because human designers rely heavily on spatial reasoning to arrange components on the chip canvas, we hypothesize that VLMs with strong visual reasoning abilities can effectively complement existing learning-based approaches. We introduce VeoPlace (Visual Evolutionary Optimization Placement), a novel framework that uses a VLM, without any fine-tuning, to guide the actions of a base placer by constraining them to subregions of the chip canvas. The VLM proposals are iteratively optimized through an evolutionary search strategy with respect to resulting placement quality. On open-source benchmarks, VeoPlace outperforms the best prior learning-based approach on 9 of 10 benchmarks with peak wirelength reductions exceeding 32%. We further demonstrate that VeoPlace generalizes to analytical placers, improving DREAMPlace performance on all 8 evaluated benchmarks with gains up to 4.3%. Our approach opens new possibilities for electronic design automation tools that leverage foundation models to solve complex physical design problems.

翻译：我们提出使用视觉语言模型（VLM）进行芯片版图规划中的宏单元布局——这一复杂优化任务近期在机器学习方法的推动下已取得显著进展。由于人类设计师在芯片画布上排布组件时高度依赖空间推理能力，我们推测具备强大视觉推理能力的VLM能有效补充现有基于学习的方法。我们提出VeoPlace（视觉进化优化布局）新框架，该框架无需微调即可利用VLM引导基础布局器的动作空间，通过将优化约束限定在芯片画布的特定子区域。VLM生成的布局方案通过进化搜索策略根据布局质量进行迭代优化。在开源基准测试中，VeoPlace在10个基准中有9个超越最佳现有学习方法，峰值线长缩减超32%。我们进一步证明VeoPlace可泛化至解析式布局器，在全部8个评估基准上均提升DREAMPlace性能，最高增益达4.3%。本方法为利用基础模型解决复杂物理设计问题的电子设计自动化工具开辟了新可能。