LLMs have recently demonstrated strong capabilities in automatic RTL code generation, achieving high syntactic and functional correctness. However, most methods focus on functional correctness while overlooking critical physical design objectives, including Power, Performance, and Area. In this work, we propose a PPA-aware, tool-integrated multi-agent framework for high-quality verilog code generation. Our framework explicitly incorporates EDA tools into a closed-loop workflow composed of a \textit{Programmer Agent}, a \textit{Correctness Agent}, and a \textit{PPA Agent}, enabling joint optimization of functional correctness and physical metrics. To support continuous improvement without model retraining, we introduce an \textit{Evolved Memory Mechanism} that externalizes optimization experience into structured memory nodes. A dedicated memory manager dynamically maintains the memory pool and allows the system to refine strategies based on historical execution trajectories. Extensive experiments demonstrate that our approach achieves strong functional correctness while delivering significant improvements in PPA metrics. By integrating tool-driven feedback with structured and evolvable memory, our framework transforms RTL generation from one-shot reasoning into a continual, feedback-driven optimization process, providing a scalable pathway for deploying LLMs in real-world hardware design flows.

翻译：近期，大语言模型在自动RTL代码生成中展现出强大能力，实现了较高的语法与功能正确性。然而，现有方法多聚焦于功能正确性，却忽视了功耗、性能与面积等关键物理设计目标。本文提出一种面向高质量Verilog代码生成的PPA感知工具集成多智能体框架。该框架将EDA工具显式融入由“程序员智能体”、“正确性智能体”和“PPA智能体”构成的闭环工作流，实现功能正确性与物理指标的联合优化。为在不进行模型重训练的前提下支持持续改进，我们引入“进化记忆机制”，将优化经验外化为结构化记忆节点。专用记忆管理器动态维护记忆池，使系统能基于历史执行轨迹优化策略。大量实验表明，本方法在保持高功能正确性的同时，显著提升了PPA指标。通过将工具驱动反馈与结构化可进化记忆相结合，本框架将RTL生成从单次推理转变为持续迭代、反馈驱动的优化过程，为LLM在实际硬件设计流程中的部署提供了可扩展路径。