Channel estimation is crucial in 5G communication networks for optimizing transmission parameters and ensuring reliable, high-speed communication. However, the use of multiple-input and multiple-output (MIMO) and millimeter-wave (mmWave) in 5G networks presents challenges in achieving accurate estimation under strict latency requirements on resource-limited hardware platforms. To address these challenges, we propose SwiftChannel, an algorithm-hardware co-design framework that integrates a hardware-friendly deep learning-based channel estimator with a dedicated accelerator. Our approach employs a convolutional neural network enhanced with a parameter-free attention mechanism, which effectively reconstructs full-resolution spatial-frequency domain channel matrices from low-resolution least squares (LS) estimates. We further develop a multi-stage model compression pipeline combining knowledge distillation, convolution re-parameterization, and quantization-aware training, resulting in substantial model size reduction with negligible accuracy loss. The hardware accelerator, implementing the compressed model and the LS estimator on FPGA platforms using High-level Synthesis (HLS), features a fine-grained pipeline architecture and optimized dataflow strategies. Tested on a Zynq UltraScale+ RFSoC, the accelerator achieves sub-millisecond latency, providing up to 24x speed-up and over 33x improvement in energy efficiency compared to GPU-based solutions. Extensive evaluations demonstrate that the proposed design generalizes not only across various noise levels and user mobilities, but also to a variety of unseen channel profiles, outperforming state-of-the-art baselines. By unifying algorithmic innovation with hardware-aware design, our work presents a future-proof channel estimation solution for 5G MIMO systems.

翻译：信道估计对于5G通信网络优化传输参数、实现可靠高速通信至关重要。然而，5G网络中多输入多输出（MIMO）与毫米波（mmWave）技术的应用，使得在资源受限硬件平台上满足严格延迟约束的同时实现精确估计面临挑战。针对上述问题，我们提出SwiftChannel算法-硬件协同设计框架，该框架集成了硬件友好的深度学习信道估计器与专用加速器。所提方法采用配备无参数注意力机制的卷积神经网络，能够从低分辨率最小二乘（LS）估计中有效重构全分辨率空频域信道矩阵。我们进一步开发了融合知识蒸馏、卷积重参数化与量化感知训练的多阶段模型压缩流水线，在精度损失可忽略的前提下实现模型体积大幅缩减。基于高层次综合（HLS）在FPGA平台上实现压缩模型与LS估计器的硬件加速器，采用细粒度流水线架构与优化数据流策略。在Zynq UltraScale+ RFSoC上的测试表明，该加速器可实现亚毫秒级延迟，较GPU方案获得高达24倍加速比和超过33倍的能效提升。大量实验证明，所提设计不仅能泛化至不同噪声水平与用户移动性场景，还可适用于多种未知信道模型，性能超越现有最优基线方案。通过算法创新与硬件感知设计的统一，本工作为5G MIMO系统提供了具备未来适应性的信道估计解决方案。