Lookup-table (LUT) based neural networks can deliver ultra-low latency and excellent hardware efficiency on FPGAs by mapping arithmetic operations directly onto the logic primitives. However, state-of-the-art LUT-aware training (LAT) approaches remain difficult to use in practice: they are often orders of magnitude slower to train than conventional networks, require non-trivial manual tuning for hardware efficiency, and lack an end-to-end workflow. This work presents HGQ-LUT, integrated in https://github.com/calad0i/HGQ2, a new LAT approach that achieves state-of-the-art hardware efficiency while accelerating training by over 100 times on modern GPUs. HGQ-LUT introduces LUT-Dense and LUT-Conv layers that are implemented with regular, accelerator-efficient tensor operations during training, which are then compiled into logic LUTs for hardware. By combining these layers with fine-grained, element-wise heterogeneous quantization (including zero-bit pruning) and a LUT-aware resource surrogate, HGQ-LUT enables the automatic exploration of accuracy-resource trade-offs without manual bit-width tuning. We further integrate HGQ-LUT into open-source toolchains, enabling unified design, compilation, and bit-exact verification of hybrid architectures that mix LUT-based with conventional arithmetic blocks. These features make LAT-based DNNs practical for real-world deployment, such as at the CERN Large Hadron Collider's experiments.

翻译：基于查找表（LUT）的神经网络通过将算术运算直接映射到逻辑原语上，能够在FPGA上实现超低延迟和卓越的硬件效率。然而，现有先进的LUT感知训练方法在实际应用中仍存在困难：其训练速度通常比传统网络慢数个数量级，需要繁琐的手动调优以实现硬件效率，且缺乏端到端工作流。本文提出HGQ-LUT（集成于https://github.com/calad0i/HGQ2），这是一种新的LAT方法，在实现最先进硬件效率的同时，在当代GPU上将训练速度提升超过100倍。HGQ-LUT引入LUT-Dense和LUT-Conv层，训练时通过常规的加速器高效张量运算实现，随后编译为硬件逻辑LUT。通过将这些层与细粒度的逐元素异构量化（包括零比特剪枝）及LUT感知资源替代模型相结合，HGQ-LUT无需手动位宽调优即可自动探索精度-资源权衡。我们进一步将HGQ-LUT集成至开源工具链，实现了混合架构（融合LUT基与传统算术模块）的统一设计、编译及精确位级验证。这些特性使基于LAT的深度神经网络在现实部署场景（如欧洲核子研究中心大型强子对撞机实验）中变得切实可行。