To mitigate the ever-worsening Power Wall problem, more and more applications need to expand their power supply to the wide-voltage range including the near-threshold region. However, the read delay distribution of the SRAM cells under the near-threshold voltage shows a more serious long-tail characteristic than that under the nominal voltage due to the process fluctuation. Such degradation of SRAM delay makes the SRAM-based cache a performance bottleneck of systems as well. To avoid the unreliable data reading, circuit-level studies use larger/more transistors in a bitcell by scarifying chip area and the static power of cache arrays. Architectural studies propose the auxiliary error correction or block disabling/remapping methods in fault-tolerant caches, which worsen both the hit latency and energy efficiency due to the complex accessing logic. This paper proposes the Timing-Speculation (TS) cache to boost the cache frequency and improve energy efficiency under low supply voltages. In the TS cache, the voltage differences of bitlines are continuously evaluated twice by a sense amplifier (SA), and the access timing error can be detected much earlier than that in prior methods. According to the measurement results from the fabricated chips, the TS L1 cache aggressively increases its frequency to 1.62X and 1.92X compared with the conventional scheme at 0.5V and 0.6V supply voltages, respectively.

翻译：为缓解日益严峻的功耗墙问题，越来越多应用需将供电范围扩展至包含近阈值区的宽电压域。然而，由于工艺波动，近阈值电压下SRAM单元的读取延迟分布相比标称电压呈现更严重的长尾特征。这种SRAM延迟退化使得基于SRAM的高速缓存成为系统性能瓶颈。为避免不可靠数据读取，电路级研究通过在位单元中使用更大/更多晶体管，但牺牲了芯片面积和缓存阵列静态功耗。架构级研究提出容错缓存中的辅助纠错或块禁用/重映射方法，但复杂访问逻辑导致命中延迟和能效均有所恶化。本文提出时序推测（TS）缓存，旨在低供电电压下提升缓存频率与能效。在TS缓存中，位线电压差由灵敏放大器连续评估两次，相比现有方法可更早检测访问时序错误。基于流片芯片的实测结果显示，在0.5V和0.6V供电电压下，TS一级缓存激进地将频率提升至传统方案的1.62倍和1.92倍。