Advanced 2.5D Systems-in-Package (SiPs) compose a growing portion of high-performance systems. While the packaging and interconnect choices play a large role in the overall system design, system architects still lack a suitable framework for early design space exploration which takes these choices into account. Current interconnect models fall mostly into the categories of 1) detailed models which are generally inflexible and require deep packaging expertise, or 2) high-level models which don't provide enough information to make accurate architectural design decisions. In this work, we present an automated chiplet IP generation framework which provides power, performance, and area estimates for various 2.5D packaging and communication configurations. The IP generator produces standard collaterals required for high-level simulation/estimation, RTL simulation, and place-and-route-level implementation (Verilog, Liberty, LEF, and datasheet). Using our framework, architects can co-optimize the package and chiplet architecture through rapid power, performance, and area estimates of various packaging strategies. As a case study, we examine generated UCIe interfaces across several packaging options.

翻译：先进2.5D系统级封装（SiPs）在高性能系统中占比日益增长。尽管封装与互连选择在整体系统设计中扮演重要角色，但系统架构师仍缺乏一个能将这些选择纳入考量的早期设计空间探索框架。当前互连模型主要分为两类：1）精细模型，通常缺乏灵活性且需要深厚的封装专业知识；2）高层次模型，无法提供足够信息以做出准确的架构设计决策。本文提出一种自动化芯片IP生成框架，可为多种2.5D封装与通信配置提供功耗、性能及面积评估。该IP生成器可产生高层次仿真/评估、RTL仿真及布局布线级实现所需的标准配套文件（Verilog、Liberty、LEF及数据手册）。通过我们的框架，架构师可基于不同封装策略的快速功耗、性能及面积评估，协同优化封装与芯片架构。作为案例研究，我们考察了跨多种封装选项生成的UCIe接口。