FPGA macro placement plays a pivotal role in routability and timing closer to the modern FPGA physical design flow. In modern FPGAs, macros could be subject to complex cascade shape constraints requiring instances to be placed in consecutive sites. In addition, in real-world FPGA macro placement scenarios, designs could have various region constraints that specify boundaries within which certain design instances and macros should be placed. In this work, we present DREAMPlaceFPGA-MP, an open-source GPU-accelerated FPGA macro-placer that efficiently generates legal placements for macros while honoring cascade shape requirements and region constraints. Treating multiple macros in a cascade shape as a large single instance and restricting instances to their respective regions, DREAMPlaceFPGA-MP obtains roughly legal placements. The macros are legalized in multiple steps to efficiently handle cascade shapes and region constraints. Our experimental results demonstrate that DREAMPlaceFPGA-MP is among the top contestants of the MLCAD 2023 FPGA Macro-Placement Contest.

翻译：FPGA宏布局在现代FPGA物理设计流程中对可布线性与时序优化起着关键作用。现代FPGA中，宏单元可能受复杂级联形状约束影响，要求实例必须放置于连续位点上。此外，在实际FPGA宏布局场景中，设计可能包含各种区域约束，限定特定设计实例与宏单元的放置边界。本文提出DREAMPlaceFPGA-MP——一款开源GPU加速FPGA宏布局器，能够在满足级联形状要求与区域约束的同时高效生成合法宏布局。通过将级联形状中的多个宏视为单个大型实例，并将实例限制在各自区域内，DREAMPlaceFPGA-MP可获得近似合法的布局。宏布局通过多步合法化流程有效处理级联形状与区域约束。实验结果表明，DREAMPlaceFPGA-MP在MLCAD 2023 FPGA宏布局竞赛中位列前茅。