Approximate computing is an emerging paradigm to improve the power and performance efficiency of error-resilient applications. As adders are one of the key components in almost all processing systems, a significant amount of research has been carried out towards designing approximate adders that can offer better efficiency than conventional designs, however, at the cost of some accuracy loss. In this paper, we highlight a new class of energy-efficient approximate adders, namely Heterogeneous Block-based Approximate Adders (HBAA), and propose a generic configurable adder model that can be configured to represent a particular HBAA configuration. An HBAA, in general, is composed of heterogeneous sub-adder blocks of equal length, where each sub-adder can be an approximate sub-adder and have a different configuration. The sub-adders are mainly approximated through inexact logic and carry truncation. Compared to the existing design space, HBAAs provide additional design points that fall on the Pareto-front and offer a better quality-efficiency trade-off in certain scenarios. Furthermore, to enable efficient design space exploration based on user-defined constraints, we propose an analytical model to efficiently evaluate the Probability Mass Function (PMF) of approximation error and other error metrics, such as Mean Error Distance (MED), Normalized Mean Error Distance (NMED) and Error Rate (ER) of HBAAs. The results show that HBAA configurations can provide around 15% reduction in area and up to 17% reduction in energy compared to state-of-the-art approximate adders.

翻译：近似计算是一种新兴范式，旨在提升容错应用的功耗与性能效率。由于加法器几乎是所有处理系统中的核心组件，大量研究致力于设计比传统方案更高效率的近似加法器，尽管这通常以牺牲一定精度为代价。本文重点介绍一类新型高能效近似加法器——异构块级近似加法器（HBAA），并提出一种通用可配置加法器模型，该模型可被配置为特定HBAA结构。HBAA通常由等长的异构子加法器块组成，每个子加法器可采用近似设计并具有不同的配置参数。子加法器的近似主要通过非精确逻辑与进位截断实现。相较于现有设计空间，HBAA提供了位于帕累托前沿上的新增设计点，在特定场景下可实现更优的质量效率权衡。此外，为基于用户约束的高效设计空间探索，我们提出一种分析模型，可高效评估HBAA的近似误差概率质量函数（PMF）及其他误差指标，如平均误差距离（MED）、归一化平均误差距离（NMED）和错误率（ER）。结果表明，相较于现有最先进的近似加法器，HBAA配置可减少约15%的面积和高达17%的能耗。