The performance of current quantum hardware is severely limited. While expanding the quantum ISA with high-fidelity, expressive basis gates is a key path forward, it imposes significant gate calibration overhead and complicates compiler optimization. As a result, even though more powerful ISAs have been designed, their use remains largely conceptual rather than practical. To move beyond these hurdles, we introduce the concept of "reconfigurable quantum instruction set computers" (ReQISC), which incorporates: (1) a unified microarchitecture capable of directly implementing arbitrary 2Q gates equivalently, i.e., SU(4) modulo 1Q rotations, with theoretically optimal gate durations given any 2Q coupling Hamiltonians; (2) a compilation framework tailored to ReQISC primitives for end-to-end synthesis and optimization, comprising a program-aware pass that refines high-level representations, a program-agnostic pass for aggressive circuit-level optimization, and an SU(4)-aware routing pass that minimizes hardware mapping overhead. We detail the hardware implementation to demonstrate the feasibility, in terms of both pulse control and calibration of this superior gate scheme on realistic hardware. By leveraging the expressivity of SU(4) and the time minimality realized by the underlying microarchitecture, the SU(4)-based ISA achieves remarkable performance, with a 4.97-fold reduction in average pulse duration to implement arbitrary 2Q gates, compared to the usual CNOT/CZ scheme on mainstream flux-tunable transmons. Supported by the end-to-end compiler, ReQISC outperforms the conventional CNOT-ISA, SOTA compiler, and pulse implementation counterparts, in significantly reducing 2Q gate counts, circuit depth, pulse duration, qubit mapping overhead, and program fidelity losses. For the first time, ReQISC makes the theoretical benefits of continuous ISAs practically feasible.

翻译：当前量子硬件的性能受到严重限制。虽然通过高保真度、表达性强的基门扩展量子指令集架构是一条关键路径，但这带来了显著的栅极校准开销并使编译器优化复杂化。因此，尽管已设计出更强大的指令集架构，其使用在很大程度上仍停留在概念层面而非实际应用。为突破这些障碍，我们提出了"可重构量子指令集计算机"的概念，该架构包含：(1) 一种统一的微架构，能够直接等效地实现任意双量子比特门，即模去单量子比特旋转的SU(4)群元，并在给定任意双量子比特耦合哈密顿量的情况下实现理论最优的栅极持续时间；(2) 一个专为ReQISC原语设计的端到端综合与优化编译框架，包括一个优化高层表示的程序感知编译阶段、一个进行激进电路级优化的程序无关编译阶段，以及一个能最小化硬件映射开销的SU(4)感知布线阶段。我们详细阐述了硬件实现方案，从脉冲控制和校准两方面论证了在现实硬件上实现这种优越栅极方案的可行性。通过利用SU(4)的表达能力和底层微架构实现的时间最优性，基于SU(4)的指令集架构取得了显著性能提升：与主流磁通可调Transmon上常用的CNOT/CZ方案相比，实现任意双量子比特门的平均脉冲持续时间减少了4.97倍。在端到端编译器的支持下，ReQISC在双量子比特门数量、电路深度、脉冲持续时间、量子比特映射开销和程序保真度损失等方面均显著优于传统的CNOT指令集架构、最先进的编译器及脉冲实现方案。ReQISC首次使连续指令集架构的理论优势具备了实际可行性。