To meet the high-speed, low-latency, and low-complexity demand for optical interconnects, simplified maximum likelihood sequence estimation (MLSE) is proposed in this paper. Simplified MLSE combines computational simplification and reduced state in MLSE. MLSE with a parallel sliding block architecture reduces latency from linear order to logarithmic order. Computational simplification reduces the number of multipliers from exponential order to linear order. Incorporating the reduced state with computational simplification further decreases the number of adders and comparators. The simplified MLSE is evaluated in a 112-Gbit/s PAM4 transmission over 2-km standard single-mode fiber. Experimental results show that the simplified MLSE significantly outperforms the FFE-only case in bit error ratio (BER) performance. Compared with simplified 1-step MLSE, the latency of simplified MLSE is reduced from 34 delay units in linear order to 7 delay units in logarithmic order. The simplified scheme in MLSE reduces the number of variable multipliers from 512 in exponential order to 33 in linear order without BER performance deterioration, while reducing the number of adders and comparators to 37.2% and 8.4%, respectively, with nearly identical BER performance.

翻译：为满足光互连对高速率、低延迟和低复杂度的需求，本文提出一种简化的最大似然序列估计（MLSE）方案。该简化MLSE融合了计算简化与状态缩减策略。采用并行滑动块架构的MLSE将延迟从线性量级降低至对数量级。计算简化使乘法器数量从指数量级降至线性量级。状态缩减与计算简化的结合进一步减少了加法器与比较器的数量。在2公里标准单模光纤的112 Gbit/s PAM4传输系统中对简化MLSE进行了性能评估。实验结果表明，在误码率（BER）性能方面，简化MLSE显著优于仅使用前馈均衡器（FFE）的方案。与简化的1步MLSE相比，简化MLSE的延迟从线性量级的34个延迟单元降至对数量级的7个延迟单元。该MLSE简化方案在保持误码率性能不变的前提下，将可变乘法器数量从指数量级的512个降至线性量级的33个，同时将加法器与比较器数量分别减少至原方案的37.2%和8.4%，且误码率性能基本保持不变。