Binary Neural Networks (BNNs) are increasingly preferred over full-precision Convolutional Neural Networks(CNNs) to reduce the memory and computational requirements of inference processing with minimal accuracy drop. BNNs convert CNN model parameters to 1-bit precision, allowing inference of BNNs to be processed with simple XNOR and bitcount operations. This makes BNNs amenable to hardware acceleration. Several photonic integrated circuits (PICs) based BNN accelerators have been proposed. Although these accelerators provide remarkably higher throughput and energy efficiency than their electronic counterparts, the utilized XNOR and bitcount circuits in these accelerators need to be further enhanced to improve their area, energy efficiency, and throughput. This paper aims to fulfill this need. For that, we invent a single-MRR-based optical XNOR gate (OXG). Moreover, we present a novel design of bitcount circuit which we refer to as Photo-Charge Accumulator (PCA). We employ multiple OXGs in a cascaded manner using dense wavelength division multiplexing (DWDM) and connect them to the PCA, to forge a novel Optical XNOR-Bitcount based Binary Neural Network Accelerator (OXBNN). Our evaluation for the inference of four modern BNNs indicates that OXBNN provides improvements of up to 62x and 7.6x in frames-per-second (FPS) and FPS/W (energy efficiency), respectively, on geometric mean over two PIC-based BNN accelerators from prior work. We developed a transaction-level, event-driven python-based simulator for evaluation of accelerators (https://github.com/uky-UCAT/B_ONN_SIM).

翻译：BNN将CNN模型参数转换为 1 位精确度, 从而可以使用简单的 XNOR 和位数操作处理 BNNN 模型参数。 这让 BNNS 能够使用硬件加速。 已经提议了一些基于 BNN 的光化集成集成电路加速器。 虽然这些加速器比电子对等器提供了极高的吞吐和能源效率, 但这些加速器中的用过的XNOR和位数电路需要进一步提高, 以改进其区域、 能源效率和吞吐量。 本文旨在满足这一需要。 为此, 我们发明了一个基于单一MRR光学的光学 XNOR 门(OXG)。 此外, 我们提出了一种新颖的位数路设计,我们称之为光源加速加速器。 我们用多OXGO- CEN- CENS- Servical Servical-alalalalal- NEVA, 我们用一个基于BNMS- 的硬度和双级硬度网络的级的级O- NXG- NAS- d Stal- Stal- dal- Studal- Stal- Stal- Stal- Stal- deval- dal- dal- deval- Stal AS- deval 和BADWA.