The validation process for microprocessors is a very complex task that consumes substantial engineering time during the design process. Bugs that degrade overall system performance, without affecting its functional correctness, are particularly difficult to debug given the lack of a golden reference for bug-free performance. This work introduces two automated performance bug localization methodologies based on machine learning that aims to aid the debugging process. Our results show that, the evaluated microprocessor core performance bugs whose average IPC impact is greater than 1%, our best-performing technique is able to localize the exact microarchitectural unit of the bug $\sim$77\% of the time, while achieving a top-3 unit accuracy (out of 11 possible locations) of over 90% for bugs with the same average IPC impact. The proposed system in our simulation setup requires only a few seconds to perform a bug location inference, which leads to a reduced debugging time.

翻译：微处理器验证过程是一项极其复杂的任务，在设计阶段耗费大量工程时间。那些降低系统整体性能但不影响功能正确性的缺陷，由于缺乏无性能缺陷的黄金参考基准，调试尤为困难。本文提出了两种基于机器学习的自动化性能缺陷定位方法，旨在辅助调试过程。结果表明，对于评估中平均IPC影响大于1%的微处理器核心性能缺陷，我们表现最佳的技术能在约77%的情况下精确定位缺陷所在的微架构单元，同时对于相同平均IPC影响的缺陷，其top-3单元准确率（共11个可能位置）超过90%。在我们的仿真环境中，提出的系统仅需数秒即可完成缺陷位置推断，从而显著缩短调试时间。