The validation process for microprocessors is a very complex task that consumes substantial engineering time during the design process. Bugs that degrade overall system performance, without affecting its functional correctness, are particularly difficult to debug given the lack of a golden reference for bug-free performance. This work introduces two automated performance bug localization methodologies based on machine learning that aims to aid the debugging process. Our results show that, the evaluated microprocessor core performance bugs whose average IPC impact is greater than 1%, our best-performing technique is able to localize the exact microarchitectural unit of the bug $\sim$77\% of the time, while achieving a top-3 unit accuracy (out of 11 possible locations) of over 90% for bugs with the same average IPC impact. The proposed system in our simulation setup requires only a few seconds to perform a bug location inference, which leads to a reduced debugging time.

翻译：验证微处理器的过程是设计过程中消耗大量工程时间的复杂任务。那些降低系统性能但不影响其功能正确性的缺陷，由于缺乏无缺陷性能的基准，尤其难以调试。本研究介绍了两种基于机器学习的自动化性能缺陷定位方法，旨在帮助调试过程。我们的结果表明，对于那些评估微处理器核心性能缺陷，其平均IPC影响大于1％的缺陷，我们最佳性能的技术可以将其准确定位到缺陷的微架构单元中，准确率约为77％，而对于具有相同平均IPC影响的缺陷，其前三个可能的位置的准确率超过90％。在我们的模拟设置中，所提出的系统仅需要几秒钟即可执行缺陷位置推理，从而缩短调试时间。