We introduce a novel logic style with self-checking capability to enhance hardware reliability at logic level. The proposed logic cells have two-rail inputs/outputs, and the functionality for each rail of outputs enables construction of faulttolerant configurable circuits. The AND and OR gates consist of 8 transistors based on CNFET technology, while the proposed XOR gate benefits from both CNFET and low-power MGDI technologies in its transistor arrangement. To demonstrate the feasibility of our new logic gates, we used an AES S-box implementation as the use case. The extensive simulation results using HSPICE indicate that the case-study circuit using on proposed gates has superior speed and power consumption compared to other implementations with error-detection capability

翻译：我们提出了一种具有自检能力的新型逻辑风格，以在逻辑层面增强硬件可靠性。所提出的逻辑单元具有双轨输入/输出，每条输出轨的功能使得构建容错可配置电路成为可能。基于CNFET技术，AND和OR门由8个晶体管构成，而所提出的XOR门在其晶体管布局中同时采用了CNFET和低功耗MGDI技术的优势。为验证新逻辑门的可行性，我们以AES S盒实现作为案例研究。使用HSPICE进行的大量仿真结果表明，与其它具有错误检测能力的实现方案相比，采用所提出逻辑门的案例电路在速度和功耗上均具有显著优势。