Driven by Moore's Law, the complexity and scale of modern chip design are increasing rapidly. Electronic Design Automation (EDA) has been widely applied to address the challenges encountered in the full chip design process. However, the evolution of very large-scale integrated circuits has made chip design time-consuming and resource-intensive, requiring substantial prior expert knowledge. Additionally, intermediate human control activities are crucial for seeking optimal solutions. In system design stage, circuits are usually represented with Hardware Description Language (HDL) as a textual format. Recently, Large Language Models (LLMs) have demonstrated their capability in context understanding, logic reasoning and answer generation. Since circuit can be represented with HDL in a textual format, it is reasonable to question whether LLMs can be leveraged in the EDA field to achieve fully automated chip design and generate circuits with improved power, performance, and area (PPA). In this paper, we present a systematic study on the application of LLMs in the EDA field, categorizing it into the following cases: 1) assistant chatbot, 2) HDL and script generation, and 3) HDL verification and analysis. Additionally, we highlight the future research direction, focusing on applying LLMs in logic synthesis, physical design, multi-modal feature extraction and alignment of circuits. We collect relevant papers up-to-date in this field via the following link: https://github.com/Thinklab-SJTU/Awesome-LLM4EDA.

翻译：受摩尔定律驱动，现代芯片设计的复杂度与规模急剧增长。电子设计自动化（EDA）已广泛应用于应对全芯片设计流程中的挑战。然而，超大规模集成电路的演进使得芯片设计耗时且资源密集，需依赖大量先验专家知识。此外，中间环节的人工控制活动对寻找最优解决方案至关重要。在系统设计阶段，电路通常以硬件描述语言（HDL）的文本形式表示。近年来，大语言模型（LLM）在上下文理解、逻辑推理与答案生成方面展现出强大能力。由于电路可通过HDL以文本形式表示，一个合理的问题是：能否将LLM应用于EDA领域，实现全自动化芯片设计，并生成具有更优功耗、性能与面积（PPA）的电路？本文系统梳理了LLM在EDA领域的应用，将其归纳为以下场景：（1）辅助聊天机器人，（2）HDL与脚本生成，以及（3）HDL验证与分析。此外，我们探讨了未来研究方向，重点关注LLM在逻辑综合、物理设计、电路多模态特征提取与对齐中的应用。我们通过以下链接收集了该领域的最新相关论文：https://github.com/Thinklab-SJTU/Awesome-LLM4EDA。