The current workloads and applications are highly diversified, facing critical challenges such as the Power Wall and the Memory Wall Problem. Different strategies over the multiple levels of Caches have evolved to mitigate these problems. Also, to work with such diversified applications, the Asymmetric Multi-Core Processor (AMP) presents itself as a viable solution. In this paper, we study the performance of L2 and Last Level Cache for different cache partitions against various AMP configurations. In addition, this study investigates the optimal cache partitioning for a collection of Multi-threaded benchmarks from PARSEC and SPLASH2 benchmark suites under medium-sized inputs. We have studied the effect of block replacement strategies and their impact on the key metrics such as total on-chip power consumption and L2 \& LLC Miss rates. Our study presents an intermediate cache design for AMPs between the two extremities of fully shared and fully private L2 \& LLC level Cache, which helps achieve the desired power values and optimal cache miss penalties.

翻译：当前的工作负载和应用高度多样化，面临着诸如功耗墙和内存墙问题等关键挑战。为缓解这些问题，多级缓存上采用了不同的策略。同时，为处理此类多样化应用，非对称多核处理器（AMP）成为一种可行的解决方案。本文研究了针对不同AMP配置，L2和最后一级缓存在不同分区下的性能。此外，本研究探讨了在中等规模输入下，来自PARSEC和SPLASH2基准测试套件的多线程基准程序集合的最优缓存分区。我们研究了块替换策略的影响及其对关键指标（如总片上功耗和L2及LLC缺失率）的作用。我们的研究为AMP提出了一种介于完全共享和完全私有的L2及LLC级缓存这两个极端之间的中间缓存设计，这有助于实现所需的功耗值和最优的缓存缺失惩罚。