Verilog's design cycle is inherently labor-intensive and necessitates extensive domain expertise. Although Large Language Models (LLMs) offer a promising pathway toward automation, their limited training data and intrinsic sequential reasoning fail to capture the strict formal logic and concurrency inherent in hardware systems. To overcome these barriers, we present EvolVE, the first framework to analyze multiple evolution strategies on chip design tasks, revealing that Monte Carlo Tree Search (MCTS) excels at maximizing functional correctness, while Idea-Guided Refinement (IGR) proves superior for optimization. We further leverage Structured Testbench Generation (STG) to accelerate the evolutionary process. To address the lack of complex optimization benchmarks, we introduce IC-RTL, targeting industry-scale problems derived from the National Integrated Circuit Contest. Evaluations establish EvolVE as the new state-of-the-art, achieving 98.1% on VerilogEval v2 and 92% on RTLLM v2. Furthermore, on the industry-scale IC-RTL suite, our framework surpasses reference implementations authored by contest participants, reducing the Power, Performance, Area (PPA) product by up to 66% in Huffman Coding and 17% in the geometric mean across all problems. The source code of the IC-RTL benchmark is available at https://github.com/weiber2002/ICRTL.

翻译：Verilog的设计周期本质上是劳动密集型的，且需要广泛的领域专业知识。尽管大语言模型（LLMs）为实现自动化提供了一条有前景的路径，但其有限的训练数据和固有的顺序推理能力难以捕捉硬件系统中严格的形化逻辑和并发性。为克服这些障碍，我们提出了EvolVE，这是首个在芯片设计任务上分析多种进化策略的框架，揭示了蒙特卡洛树搜索（MCTS）在最大化功能正确性方面表现卓越，而思想引导精炼（IGR）在优化方面更具优势。我们进一步利用结构化测试平台生成（STG）来加速进化过程。针对复杂优化基准的缺乏，我们引入了IC-RTL，其目标源自全国集成电路设计竞赛的工业规模问题。评估结果表明，EvolVE确立了新的最先进水平，在VerilogEval v2上达到98.1%，在RTLLM v2上达到92%。此外，在工业规模的IC-RTL测试套件上，我们的框架超越了竞赛参与者编写的参考实现，在哈夫曼编码中将功耗、性能、面积（PPA）乘积降低了高达66%，在所有问题的几何平均上降低了17%。IC-RTL基准的源代码可在https://github.com/weiber2002/ICRTL获取。