We discuss a nondeterministic variant of the recently introduced machine model of deterministic auxiliary depth-$k$ storage automata (or aux-$k$-sda's) by Yamakami. It was proven that all languages recognized by polynomial-time logarithmic-space aux-$k$-sda's are located between $\mathrm{LOGDCFL}$ and $\mathrm{SC}^k$ (the $k$th level of Steve's class SC). We further propose a new and simple computational model of semi-unbounded fan-in Boolean circuits composed partly of cascading blocks, in which the first few AND gates of unbounded fan-out (called AND$_{(\omega)}$ gates) at each layer from the left (where all gates at each layer are indexed from left to right) are linked in a "cascading" manner to their right neighbors though specific AND and OR gates. We use this new circuit model to characterize a nondeterministic variant of the aux-$2k$-sda's (called aux-$2k$-sna's) that run in polynomial time using logarithmic work space. By relaxing the requirement for cascading circuits, we also demonstrate how such cascading circuit families characterize the complexity class $\mathrm{P}$. This yields an upper bound on the computational complexity of $\mathrm{LOG}k\mathrm{SNA}$ by $\mathrm{P}$.

翻译：我们讨论了由 Yamakami 最近提出的确定性辅助深度-$k$ 存储自动机（或称 aux-$k$-sda）模型的一种非确定性变体。已有证明表明，所有由多项式时间对数空间 aux-$k$-sda 识别的语言都位于 $\mathrm{LOGDCFL}$ 和 $\mathrm{SC}^k$（Steve 类 SC 的第 $k$ 层）之间。我们进一步提出了一种新的、简单的半无界扇入布尔电路计算模型，该模型部分由级联块组成。在该模型中，每一层（其中每层的所有门从左到右索引）左侧的前几个无界扇出 AND 门（称为 AND$_{(\omega)}$ 门）通过特定的 AND 门和 OR 门以“级联”方式与其右侧邻居相连。我们利用这一新的电路模型来刻画一类在多项式时间内运行并使用对数工作空间的 aux-$2k$-sda 的非确定性变体（称为 aux-$2k$-sna）。通过放宽对级联电路的要求，我们还展示了此类级联电路族如何刻画复杂度类 $\mathrm{P}$。这得到了 $\mathrm{LOG}k\mathrm{SNA}$ 的计算复杂度的一个上界 $\mathrm{P}$。