While transistor density is still increasing, clock speeds are not, motivating the search for new parallel architectures. One approach is to completely abandon the concept of CPU -- and thus serial imperative programming -- and instead to specify and execute tasks in parallel, compiling from programming languages to data flow digital logic. It is well-known that pure functional languages are inherently parallel, due to the Church-Rosser theorem, and CPU-based parallel compilers exist for many functional languages. However, these still rely on conventional CPUs and their von Neumann bottlenecks. An alternative is to compile functional languages directly into digital logic to maximize available parallelism. It is difficult to work with complete modern functional languages due to their many features, so we demonstrate a proof-of-concept system using lambda calculus as the source language and compiling to digital logic. We show how functional hardware can be tailored to a simplistic functional language, forming the ground for a new model of CPU-less functional computation. At the algorithmic level, we use a tree-based representation, with data localized within nodes and communicated data passed between them. This is implemented by physical digital logic blocks corresponding to nodes, and buses enabling message passing. Node types and behaviors correspond to lambda grammar forms, and beta-reductions are performed in parallel allowing branches independent from one another to perform transformations simultaneously. As evidence for this approach, we present an implementation, along with simulation results, showcasing successful execution of lambda expressions. This suggests that the approach could be scaled to larger functional languages. Successful execution of a test suite of lambda expressions suggests that the approach could be scaled to larger functional languages.

翻译：尽管晶体管密度仍在持续增长，时钟频率却未能同步提升，这推动了对新型并行架构的探索。一种解决方案是彻底摒弃CPU的概念——以及与之相关的串行指令式编程范式——转而采用并行方式描述和执行任务，将编程语言编译为数据流数字逻辑。众所周知，由于Church-Rosser定理的存在，纯函数式语言天然具备并行特性，目前已有多种基于CPU的并行编译器支持各类函数式语言。然而，这些方案仍依赖于传统CPU及其冯·诺依曼瓶颈。另一种替代方案是将函数式语言直接编译为数字逻辑，以最大化利用可用并行性。由于现代完整函数式语言功能特性复杂，直接处理较为困难，因此我们采用Lambda演算作为源语言，通过编译至数字逻辑的方式构建了一个概念验证系统。我们展示了如何为简化函数式语言定制函数式硬件，从而为新型无CPU函数式计算模型奠定基础。在算法层面，我们采用基于树的表示方法，数据封装于节点内部，通信数据通过节点间传递实现。该系统通过物理数字逻辑模块对应节点，并利用总线实现消息传递。节点类型和行为对应Lambda语法结构，β归约操作以并行方式执行，使得相互独立的分支能够同时进行变换。为验证该方法的可行性，我们提供了具体实现及仿真结果，展示了Lambda表达式的成功执行过程。实验结果表明，该方法具备向更复杂函数式语言扩展的潜力。测试用例集中的Lambda表达式均成功执行，进一步证明该方案可扩展至更大型的函数式语言。