Adders are fundamental building blocks in modern digital systems, and their performance, power, and area (PPA) directly impact system efficiency. Contemporary adders typically use parallel-prefix architectures with established PPA trade-offs, but these often fail to deliver globally optimal PPA for specific design goals. Prior work lacks netlist-/cell-level awareness, and general synthesis heuristics are not adder-specific, resulting in suboptimal PPA. To address this, we propose AXON, an automated netlist optimization framework for adders. It performs design space exploration from architectural to netlist level, integrating prefix topology search with standard-cell-aware mapping via a hierarchical approach to quickly converge to near-optimal PPA solutions. We also introduce a hybrid ultra-high-speed adder combining parallel-prefix and Ling architectures to shorten the critical path. Experiments on TSMC 28nm library show AXON improves delay, area-delay product, and energy-delay product by up to 10.3%, 12.6%, and 32.1% respectively, compared to commercial synthesis tools.

翻译：摘要：加法器是现代数字系统中的基础构件，其性能、功耗与面积（PPA）直接影响系统效率。当代加法器通常采用具有既定PPA权衡关系的并行前缀架构，但这些架构往往无法针对特定设计目标实现全局最优的PPA。现有工作缺乏对网表级/单元级的感知能力，且通用综合启发式算法不具备加法器特异性，导致PPA次优。为此，我们提出AXON——一种面向加法器的自动化网表优化框架。该框架执行从架构级到网表级的设计空间探索，通过分层方法集成前缀拓扑搜索与标准单元感知映射，从而快速收敛至近最优PPA解。我们还引入了一种结合并行前缀与Ling架构的混合型超高速加法器，以缩短关键路径。基于台积电28纳米库的实验表明，与商业综合工具相比，AXON在延迟、面积-延迟积和能耗-延迟积上分别实现了最高10.3%、12.6%和32.1%的改进。