Hardware generators help designers explore families of concrete designs and their efficiency trade-offs. Both parameterized hardware description languages (HDLs) and higher-level programming models, however, can obstruct composability. Different concrete designs in a family can have dramatically different timing behavior, and high-level hardware generators rarely expose a consistent HDL-level interface. Composition, therefore, is typically only feasible at the level of individual instances: the user generates concrete designs and then composes them, sacrificing the ability to parameterize the combined design. We design Parafil, a system for correctly composing hardware generators. Parafil builds on Filament, an HDL with strong compile-time guarantees, and lifts those guarantees to generators to prove that all possible instantiations are free of timing bugs. Parafil can integrate with external hardware generators via a novel system of output parameters and a framework for invoking generator tools. We conduct experiments with two other generators, FloPoCo and Google's XLS, and we implement a parameterized FFT generator to show that Parafil ensures correct design space exploration.

翻译：硬件生成器帮助设计人员探索具体设计系列及其效率权衡。然而，参数化硬件描述语言和高级编程模型都可能阻碍可组合性。同一系列中的不同具体设计可能具有截然不同的时序行为，而高级硬件生成器很少公开一致的HDL级接口。因此，组合通常只能在单个实例层面实现：用户生成具体设计然后进行组合，从而牺牲了组合设计的参数化能力。我们设计了Parafil——一个用于正确组合硬件生成器的系统。Parafil基于Filament（一种具备强编译时保证的硬件描述语言），并将这些保证提升至生成器层面，以证明所有可能的实例化均无时序错误。Parafil通过新颖的输出参数系统和生成器工具调用框架，可与外部硬件生成器集成。我们使用另外两个生成器（FloPoCo和Google的XLS）进行实验，并实现了参数化的FFT生成器，以证明Parafil能够确保正确的设计空间探索。