The Vienna Architecture Description Language (VADL) is a powerful processor description language (PDL) that enables the concise formal specification of processor architectures. By utilizing a single VADL processor specification, the VADL system exhibits the capability to automatically generate a range of artifacts necessary for rapid design space exploration. These include assemblers, compilers, linkers, functional instruction set simulators, cycle-accurate instruction set simulators, synthesizable specifications in a hardware description language, as well as test cases and documentation. One distinctive feature of VADL lies in its separation of the instruction set architecture (ISA) specification and the microarchitecture (MiA) specification. This segregation allows users the flexibility to combine various ISAs with different MiAs, providing a versatile approach to processor design. In contrast to existing PDLs, VADL's MiA specification operates at a higher level of abstraction, enhancing the clarity and simplicity of the design process. Notably, with a single ISA specification, VADL streamlines compiler generation and maintenance by eliminating the need for intricate compiler-specific knowledge. This article introduces VADL, describes the generator techniques in detail and demonstrates the power of the language and the performance of the generators in an empirical evaluation. The evaluation shows the expressiveness and conciseness of VADL and the efficiency of the generated artifacts.

翻译：维也纳架构描述语言（VADL）是一种强大的处理器描述语言（PDL），能够简洁地形式化规范处理器架构。通过使用单一的VADL处理器规范，VADL系统能够自动生成一系列支持快速设计空间探索的必要构件，包括汇编器、编译器、链接器、功能级指令集模拟器、周期精确指令集模拟器、硬件描述语言中的可综合规范，以及测试用例和文档。VADL的独特特征在于其将指令集架构（ISA）规范与微架构（MiA）规范相分离。这种分离允许用户灵活地将不同ISA与不同MiA组合，提供了一种多功能的处理器设计方法。与现有PDL相比，VADL的MiA规范在更高抽象层级上运行，增强了设计过程的清晰度和简洁性。值得注意的是，通过单一的ISA规范，VADL无需用户具备复杂的编译器专业知识即可简化编译器的生成与维护。本文介绍VADL，详细描述生成器技术，并通过实证评估展示该语言的能力及生成器的性能。评估结果显示了VADL的表达力与简洁性，以及生成构件的效率。