With Large Language Models (LLMs) recently demonstrating impressive proficiency in code generation, it is promising to extend their abilities to Hardware Description Language (HDL). However, LLMs tend to generate single HDL code blocks rather than hierarchical structures for hardware designs, leading to hallucinations, particularly in complex designs like Domain-Specific Accelerators (DSAs). To address this, we propose HiVeGen, a hierarchical LLM-based Verilog generation framework that decomposes generation tasks into LLM-manageable hierarchical submodules. HiVeGen further harnesses the advantages of such hierarchical structures by integrating automatic Design Space Exploration (DSE) into hierarchy-aware prompt generation, introducing weight-based retrieval to enhance code reuse, and enabling real-time human-computer interaction to lower error-correction cost, significantly improving the quality of generated designs.

翻译：随着大型语言模型（LLM）近期在代码生成方面展现出卓越能力，将其能力扩展至硬件描述语言（HDL）领域具有广阔前景。然而，LLM倾向于生成单一HDL代码块而非硬件设计所需的分层结构，这容易导致生成结果出现幻觉问题，在领域专用加速器（DSA）等复杂设计中尤为明显。为解决这一问题，我们提出HiVeGen——一个基于LLM的分层Verilog生成框架，该框架将生成任务分解为LLM可管理的分层子模块。HiVeGen进一步通过以下方式利用分层结构的优势：将自动设计空间探索（DSE）集成至层次感知的提示生成中，引入基于权重的检索机制以增强代码复用能力，并支持实时人机交互以降低错误修正成本，从而显著提升生成设计的质量。