This project develops a pseudo-random number generator (PRNG) using the logistic map, implemented in Verilog HDL on an FPGA and processes its output through a Central Limit Theorem (CLT) function to achieve a Gaussian distribution. The system integrates additional FPGA modules for real-time interaction and visualisation, including a clock generator, UART interface, XADC, and a 7-segment display driver. These components facilitate the direct display of PRNG values on the FPGA and the transmission of data to a laptop for histogram analysis, verifying the Gaussian nature of the output. This approach demonstrates the practical application of chaotic systems for generating Gaussian-distributed pseudo-random numbers in digital hardware, highlighting the logistic map's potential in PRNG design.

翻译：本项目采用逻辑斯蒂映射设计了一种伪随机数生成器（PRNG），并在FPGA上通过Verilog HDL实现，其输出经中心极限定理（CLT）函数处理后获得高斯分布。系统集成了额外的FPGA模块以实现实时交互与可视化，包括时钟生成器、UART接口、XADC以及七段数码管驱动模块。这些组件可让PRNG值在FPGA上直接显示，同时将数据传输至笔记本电脑进行直方图分析，从而验证输出的高斯特性。该方法展示了混沌系统在数字硬件中生成高斯分布伪随机数的实际应用，凸显了逻辑斯蒂映射在PRNG设计中的潜力。