Recently, progress has been made on the Intra Pattern Copy (IPC) tool for JPEG XS, an image compression standard designed for low-latency and low-complexity coding. IPC performs wavelet-domain intra compensation predictions to reduce spatial redundancy in screen content. A key module of IPC is the displacement vector (DV) search, which aims to solve the optimal prediction reference offset. However, the DV search process is computationally intensive, posing challenges for practical hardware deployment. In this paper, we propose an efficient pipelined FPGA architecture design for the DV search module to promote the practical deployment of IPC. Optimized memory organization, which leverages the IPC computational characteristics and data inherent reuse patterns, is further introduced to enhance the performance. Experimental results show that our proposed architecture achieves a throughput of 38.3 Mpixels/s with a power consumption of 277 mW, demonstrating its feasibility for practical hardware implementation in IPC and other predictive coding tools, and providing a promising foundation for ASIC deployment.

翻译：近年来，面向低延迟、低复杂度编码的图像压缩标准JPEG XS中的帧内模式拷贝工具取得了进展。IPC通过执行小波域帧内补偿预测来降低屏幕内容的空间冗余。IPC的一个关键模块是位移矢量搜索，其旨在求解最优预测参考偏移量。然而，DV搜索过程计算密集，对实际硬件部署提出了挑战。本文为DV搜索模块提出了一种高效的流水线FPGA架构设计，以促进IPC的实际部署。进一步引入了优化的存储器组织方案，该方案利用IPC的计算特性和数据固有的重用模式，以提升性能。实验结果表明，所提架构的吞吐率达到38.3兆像素/秒，功耗为277毫瓦，证明了其在IPC及其他预测编码工具中实际硬件实现的可行性，并为ASIC部署提供了良好基础。