We introduce an approach to designing FPGA-accelerated middleboxes that simplifies development, debugging, and performance tuning by decoupling the tasks of hardware-accelerator implementation and software-application programming. Rosebud is a framework that links hardware accelerators to a high-performance packet processing pipeline through a standardized hardware/software interface. This separation of concerns allows hardware developers to focus on optimizing custom accelerators while freeing software programmers to reuse, configure, and debug accelerators in a fashion akin to software libraries. We show the benefits of the Rosebud framework by building a firewall based on a large blacklist and porting the Pigasus IDS pattern-matching accelerator in less than a month. Our experiments demonstrate that Rosebud delivers high performance, serving ~200 Gbps of traffic while adding only 0.7-7 microseconds of latency.

翻译：摘要：我们提出了一种设计FPGA加速中间盒的方法，通过解耦硬件加速器实现与软件应用编程的任务，简化了开发、调试和性能调优过程。Rosebud是一个框架，它通过标准化的硬件/软件接口将硬件加速器与高性能数据包处理流水线相连接。这种关注点分离使硬件开发者能够专注于优化自定义加速器，同时让软件程序员能够像使用软件库一样复用、配置和调试加速器。我们通过基于大规模黑名单构建防火墙，并在一个月内移植Pigasus入侵检测系统模式匹配加速器，展示了Rosebud框架的优势。实验证明，Rosebud实现了高性能，可处理约200 Gbps的流量，仅增加0.7至7微秒的延迟。