With the rise of Deep Learning (DL), our world braces for AI in every edge device, creating an urgent need for edge-AI SoCs. This SoC hardware needs to support high throughput, reliable and secure AI processing at Ultra Low Power (ULP), with a very short time to market. With its strong legacy in edge solutions and open processing platforms, the EU is well-positioned to become a leader in this SoC market. However, this requires AI edge processing to become at least 100 times more energy-efficient, while offering sufficient flexibility and scalability to deal with AI as a fast-moving target. Since the design space of these complex SoCs is huge, advanced tooling is needed to make their design tractable. The CONVOLVE project (currently in Inital stage) addresses these roadblocks. It takes a holistic approach with innovations at all levels of the design hierarchy. Starting with an overview of SOTA DL processing support and our project methodology, this paper presents 8 important design choices largely impacting the energy efficiency and flexibility of DL hardware. Finding good solutions is key to making smart-edge computing a reality.

翻译：随着深度学习（DL）的兴起，我们的世界正迎接每一台边缘设备中的人工智能，这催生了对边缘AI片上系统（SoC）的迫切需求。这种SoC硬件需要在超低功耗（ULP）下支持高吞吐量、可靠且安全的AI处理，同时实现极短的市场投放时间。凭借其在边缘解决方案和开放处理平台领域的深厚积淀，欧盟具备成为该SoC市场领导者的有利条件。然而，这要求AI边缘处理的能效提升至少100倍，同时保持足够的灵活性和可扩展性以应对AI这一快速发展的目标。由于这些复杂SoC的设计空间极为庞大，需要先进的工具才能使其设计变得易于处理。CONVOLVE项目（目前处于初始阶段）正是为了解决这些障碍。它采用整体方法，在设计层级的所有层面进行创新。本文从当前最先进的深度学习处理支持概述及我们的项目方法论入手，提出了8个对深度学习硬件能效和灵活性具有重大影响的关键设计选择。找到良好解决方案是实现智能边缘计算的关键。