Circuit design based on Quantum-dots Cellular Automata technology offers power-efficiency and nano-size circuits. It is an attractive alternative to CMOS technology. The XOR gate is a widely used building element in arithmetic circuits. An efficient XOR gate in QCA computational circuits can significantly improve efficiency. This paper proposes two different approaches for designing 3-input QCA XOR gates with 10 and 8 cells. They require two clock phases to create output. They have efficient and scalable structures. To demonstrate the functionality of these structures, we design QCA full adders using the suggested gates and compare the results with existing designs. The proposed QCA full adder has only 12 cells and is the best compared to all the existing counterparts. We simulated and verified the proposed structures. We proved the functionality of the proposed QCA full adder and the suggested QCA XOR structures. Additionally, QCAPro is used to estimate the energy dissipation of the proposed XOR and Full-adder. The results demonstrated that the proposed designs have the desired performance based on the number of cells, occupied area, and latency.

翻译：基于量子点元胞自动机技术的电路设计具有高能效和纳米级尺寸的优势，是CMOS技术的有力替代方案。异或门是算术电路中广泛使用的基础元件，在QCA计算电路中实现高效异或门可显著提升效率。本文提出两种不同的三输入QCA异或门设计方案，分别采用10个和8个量子点元胞，仅需两个时钟相位即可生成输出，具有高效且可扩展的结构。为验证这些结构的可行性，我们利用所提出的异或门设计了QCA全加器，并与现有设计方案进行对比。本文提出的QCA全加器仅需12个元胞，性能优于现有同类设计。我们通过仿真验证了所提结构的功能，证明了QCA全加器及异或门结构的正确性。此外，采用QCAPro工具估算了所提异或门与全加器的能耗。结果表明，基于元胞数量、占用面积和延迟等指标，所提设计方案具有理想性能。