A system can satisfy accuracy-based validation, maintain output stability (Safety-Threshold Exceedance Rate, STER, equal to zero), and still violate timing constraints under deployment load. These are structurally independent properties that current pre-market validation protocols often do not operationalize at the inference layer. This letter demonstrates their independence through a controlled same-hardware experiment: identical MobileNetV2 models are evaluated under identical adversarial load on two execution paths of the same NVIDIA Jetson Orin Nano Super, a dedicated GPU accelerator (TensorRT FP16, half-precision floating point) and a general-purpose CPU (ONNX Runtime FP32, single-precision floating point). Both paths maintain STER = 0; the CPU path (ONNX Runtime FP32) degrades 7.2x under combined load (mean latency 9.8x higher than the GPU path (TensorRT FP16), which maintains latency below 11 ms), breaching the 10 Hz clinical cycle budget by 65%. Joint STER and latency verification is proposed as a candidate method for operationalizing U.S. FDA Draft Guidance FDA-2024-D-4488 robustness requirements at the inference layer, subject to regulatory review and clinical validation.

翻译：系统可以满足基于精度的验证、保持输出稳定性（安全阈值超出率STER=0），但在部署负载下仍可能违反时序约束。这些结构上独立的属性，当前上市前验证协议通常未在推理层加以落实。本论文通过受控同硬件实验证明了这种独立性：在相同NVIDIA Jetson Orin Nano Super平台的两个执行路径——专用GPU加速器（TensorRT FP16半精度浮点）与通用CPU（ONNX Runtime FP32单精度浮点）——上，对相同的MobileNetV2模型在相同对抗负载下进行评估。两条路径均保持STER=0；CPU路径（ONNX Runtime FP32）在组合负载下退化7.2倍（平均延迟比GPU路径（TensorRT FP16）高9.8倍，后者保持延迟低于11毫秒），超出10Hz临床周期预算65%。本文提出联合STER与延迟验证作为在推理层落实美国FDA指南草案FDA-2024-D-4488稳健性要求的候选方法，该方案有待监管审查与临床验证。