This paper addresses the design of a partly-parallel cascaded FFT-IFFT architecture that does not require any intermediate buffer. Folding can be used to design partly-parallel architectures for FFT and IFFT. While many cascaded FFT-IFFT architectures can be designed using various folding sets for the FFT and the IFFT, for a specified folded FFT architecture, there exists a unique folding set to design the IFFT architecture that does not require an intermediate buffer. Such a folding set is designed by processing the output of the FFT as soon as possible (ASAP) in the folded IFFT. Elimination of the intermediate buffer reduces latency and saves area. The proposed approach is also extended to interleaved processing of multi-channel time-series. The proposed FFT-IFFT cascade architecture saves about N/2 memory elements and N/4 clock cycles of latency compared to a design with identical folding sets. For the 2-interleaved FFT-IFFT cascade, the memory and latency savings are, respectively, N/2 units and N/2 clock cycles, compared to a design with identical folding sets.

翻译：本文研究了一种无需中间缓冲器的部分并行级联FFT-IFFT架构设计。折叠技术可用于设计FFT和IFFT的部分并行架构。虽然通过为FFT和IFFT采用不同的折叠集可以设计多种级联FFT-IFFT架构，但对于特定的折叠FFT架构，存在唯一确定的折叠集，使得IFFT架构无需中间缓冲器。该折叠集的设计原则是在折叠IFFT中尽可能快地处理FFT的输出。消除中间缓冲器可降低延迟并节省面积。所提方法还扩展至多通道时间序列的交错处理。与采用相同折叠集的设计相比，所提FFT-IFFT级联架构可节省约N/2个存储单元和N/4个时钟周期的延迟。对于2路交错FFT-IFFT级联，与采用相同折叠集的设计相比，存储和延迟节省量分别为N/2个单元和N/2个时钟周期。