With the slowing down of Moore's law, augmenting complementary-metal-oxide semiconductor (CMOS) transistors with emerging nanotechnologies (X) is becoming increasingly important. In this paper, we demonstrate how stochastic magnetic tunnel junction (sMTJ)-based probabilistic bits, or p-bits, can be combined with versatile Field Programmable Gate Arrays (FPGA) to design an energy-efficient, heterogeneous CMOS + X (X = sMTJ) prototype. Our heterogeneous computer successfully performs probabilistic inference and asynchronous Boltzmann learning despite device-to-device variations in sMTJs. A comprehensive comparison using a CMOS predictive process design kit (PDK) reveals that digital CMOS-based p-bits emulating high-quality randomness use over 10,000 transistors with the energy per generated random number being roughly two orders of magnitude greater than the sMTJ-based p-bits that dissipate only 2 fJ. Scaled and integrated versions of our approach can significantly advance probabilistic computing and its applications in various domains, including probabilistic machine learning, optimization, and quantum simulation.

翻译：随着摩尔定律的放缓，用新兴纳米技术（X）增强互补金属氧化物半导体（CMOS）晶体管正变得日益重要。本文展示了如何将基于随机磁隧道结（sMTJ）的概率比特（即p-bit）与多功能现场可编程门阵列（FPGA）相结合，设计出一款高能效的异构CMOS + X（X = sMTJ）原型机。尽管sMTJ存在器件间差异，我们的异构计算机仍成功执行了概率推理与异步玻尔兹曼学习。使用CMOS预测工艺设计套件（PDK）进行的全面对比表明，基于数字CMOS的p比特在模拟高质量随机性时需消耗超过10,000个晶体管，且每个随机数生成的能量约为仅耗散2 fJ的sMTJ型p比特的两个数量级。该方法的规模化与集成化版本将显著推动概率计算及其在概率机器学习、优化及量子模拟等领域的应用。