Large Language Models (LLMs) have demonstrated significant potential in various engineering tasks, including software development, digital logic generation, and companion document maintenance. However, their ability to perform board-level circuit design is understudied, as this task requires a synergized understanding of real-world physics and Integrated Circuit (IC) datasheets, the latter comprising detailed specifications for individual components. To address this challenge, we propose \hweb, an evaluation framework that benchmarks the ability of LLMs to perform such designs. It consists of 300 board-level design tasks pulled from open-source and crowdsourcing platforms such as GitHub and OSHWLab, covering 8 application domains, and is complemented with a knowledge base of 2,914 real IC datasheets. For each task, the LLMs are tasked with generating a schematic from scratch, using the provided circuit functional requirements and a set of component datasheets as input. The resulting schematic will be checked against a static electrical rules, and then passed to a circuit simulator to verify its dynamic behavior. Our evaluation show that although current models achieve initial engineering usability and documentation understanding, they lack physical intuition, as the top-performing model achieved an overall pass rate of 8.15\%. We envision that advancements on \hweb\ will pave the way for the development of practical Electronic Design Automation (EDA) agents, revolutionizing the field of board-level design.

翻译：大型语言模型（LLMs）在各类工程任务中展现出巨大潜力，包括软件开发、数字逻辑生成及配套文档维护。然而，其在板级电路设计方面的能力尚未充分研究——该任务需要结合对真实物理世界的理解与集成电路（IC）数据手册（后者包含各元件的详细规格）。为应对这一挑战，我们提出\hweb评估框架，用于基准测试LLM执行此类设计的水平。该框架包含从GitHub、OSHWLab等开源及众包平台收集的300项板级设计任务，覆盖8个应用领域，并配备包含2,914份真实IC数据手册的知识库。针对每项任务，LLM需根据提供的电路功能需求及一组元件数据手册，从零开始生成原理图。生成的原理图将先通过静态电气规则检查，再经电路仿真验证其动态行为。评估表明，尽管当前模型已具备初步工程可用性与文档理解能力，但缺乏物理直觉——性能最优模型的整体通过率仅为8.15%。我们预计，基于\hweb的突破性进展将为开发实用型电子设计自动化（EDA）智能体铺平道路，并革新板级设计领域。