Circuit cutting is a promising technique that leverages both quantum and classical computational resources, enabling the practical execution of large quantum circuits on noisy intermediate-scale quantum (NISQ) hardware. Recent approaches typically focus exclusively on either gate cuts or wire cuts, modeling quantum circuits as graphs. However, identifying optimal cutting locations using this representation often results in prohibitively high computational complexity, especially under realistic hardware constraints. In this paper, we introduce CIFOLD, a novel graph-based framework that exploits repetitive modular structures inherent in quantum algorithms, significantly enhancing the scalability and efficiency of circuit cutting. Our approach systematically folds quantum circuits into compact meta-graphs by identifying and merging common gate sequences across entangled qubits, dramatically simplifying subsequent partitioning tasks. We define folding factor and variance to quantify circuit compression and ensure balanced folding. Using these condensed representations, CIFOLD precisely identifies cut locations without exhaustive global graph searches. We perform extensive experiments, comparing CIFOLD with state-of-the-art circuit-cutting techniques. Results demonstrate that CIFOLD achieves superior partition quality and computational efficiency, reducing the number of required cuts by an average of 31.6% and lowering the sampling overhead substantially by 3.55*10^9. Our findings illustrate that CIFOLD represents a significant advancement toward scalable quantum circuit cutting.
翻译:电路切割是一种有前景的技术,它同时利用量子与经典计算资源,使得在噪声中等规模量子(NISQ)硬件上实际执行大规模量子电路成为可能。近期方法通常仅专注于门切割或线切割,将量子电路建模为图。然而,基于这种表示确定最优切割位置往往导致极高的计算复杂度,尤其是在实际硬件约束下。本文提出CIFOLD,一种新颖的基于图框架,利用量子算法中固有的重复模块化结构,显著提升了电路切割的可扩展性和效率。我们的方法通过识别并合并纠缠量子比特间的公共门序列,系统地将量子电路折叠为紧凑的元图,极大简化了后续的分区任务。我们定义了折叠因子和方差以量化电路压缩并确保平衡折叠。利用这些压缩表示,CIFOLD无需进行穷举全局图搜索即可精确识别切割位置。我们进行了大量实验,将CIFOLD与最先进的电路切割技术进行对比。结果表明,CIFOLD实现了更优的分区质量和计算效率,平均减少所需切割次数31.6%,并将采样开销大幅降低3.55×10^9。我们的发现表明,CIFOLD代表了迈向可扩展量子电路切割的重要进展。