This paper presents a hybrid decoding architecture that serially couples a normalized min-sum (NMS) decoder with reinforced ordered statistics decoding (OSD) to achieve near-maximum likelihood (ML) performance for short linear block codes, including LDPC, BCH, and RS codes. The framework introduces several key innovations. A decoding information aggregation model based on a convolutional neural network refines bit-reliability estimates for OSD using the soft-output trajectory of the NMS decoder. An adaptive decoding path for OSD is initialized by the arranged list of the most a priori likely tests algorithm and dynamically updated with empirical data. A sliding-window assisted model enables early termination of test error pattern (TEP) traversal, reducing complexity with minimal performance loss. For short high-rate codes, an undetected error detector identifies erroneous NMS outputs that satisfy parity checks, ensuring they are forwarded to OSD for correction. Extensive simulations on LDPC, BCH, and RS codes demonstrate that the proposed hybrid decoder achieves a competitive trade-off: near-ML frame error rate performance while maintaining advantages in throughput, latency, and complexity over state-of-the-art alternatives. Complexity analysis shows that the average number of OSD TEPs is drastically reduced, and the architecture remains highly parallelizable. An optimization framework is also formulated to balance performance and complexity via parameter tuning.

翻译：本文提出一种混合译码架构，将归一化最小和（NMS）译码器与增强型有序统计译码（OSD）串行耦合，以实现短线性分组码（包括LDPC、BCH和RS码）的近最大似然（ML）性能。该框架引入多项关键创新：基于卷积神经网络的译码信息聚合模型，利用NMS译码器的软输出轨迹为OSD优化比特可靠性估计；采用最优先验似然测试算法的排列列表初始化OSD的自适应译码路径，并通过经验数据动态更新；滑动窗口辅助模型支持测试错误模式（TEP）遍历的提前终止，以最小性能损失降低复杂度。针对短高码率码，未检测错误检测器可识别满足奇偶校验却译码错误的NMS输出，确保其被转发至OSD进行校正。对LDPC、BCH和RS码的广泛仿真表明，所提混合译码器实现了具有竞争力的权衡：在保持近ML帧错误率性能的同时，相较于现有先进方法，在吞吐量、时延和复杂度方面具有优势。复杂度分析显示，OSD的平均TEP数量大幅减少，且架构保持高度可并行化。此外，本文还构建了通过参数调优平衡性能与复杂度的优化框架。