High-Level Synthesis (HLS) is a pivotal electronic design automation (EDA) technology that enables the generation of hardware circuits from high-level language descriptions. A critical step in HLS is Design Space Exploration (DSE), which seeks to identify high-quality hardware architectures under given constraints. However, the enormous size of the design space makes DSE computationally prohibitive. Although numerous algorithms have been proposed to accelerate DSE, our extensive experimental studies reveal that no single algorithm consistently achieves Pareto dominance across all problem instances. Consequently, the inability of any single algorithm to dominate all benchmarks necessitates an automated selection mechanism to identify the best-performing DSE algorithm for each specific case. To address this challenge, we propose the SoberDSE framework, which recommends suitable algorithm based on benchmark characteristics. Experimental results demonstrate that our SoberDSE framework significantly outperforms state-of-the-art heuristic-based DSE algorithms by up to 5.7 $\times$ and state-of-the-art learning-based DSE methods by up to 4.2 $\times$. Furthermore, compared to conventional classification models, SoberDSE delivers superior accuracy in small-sample learning scenarios, with an average enhancement of 35.57\%. Code and models are available at https://anonymous.4open.science/r/Sober-4377.

翻译：高层次综合（High-Level Synthesis，HLS）是一项关键的电子设计自动化（EDA）技术，能够从高级语言描述生成硬件电路。HLS中的一个关键步骤是设计空间探索（Design Space Exploration，DSE），其目标是在给定约束条件下寻找高质量的硬件架构。然而，设计空间的巨大规模使得DSE在计算上难以承受。尽管已有大量算法被提出以加速DSE，我们广泛的实验研究表明，没有单一算法能够在所有问题实例上持续保持帕累托优势。因此，由于任何单一算法都无法在所有基准测试中占优，需要一种自动选择机制来为每个具体案例识别性能最佳的DSE算法。为应对这一挑战，我们提出了SoberDSE框架，该框架根据基准测试特征推荐合适的算法。实验结果表明，我们的SoberDSE框架显著优于最先进的基于启发式的DSE算法，最高可达5.7倍；同时优于最先进的基于学习的DSE方法，最高可达4.2倍。此外，与传统分类模型相比，SoberDSE在小样本学习场景下展现出更优的准确率，平均提升达35.57%。代码与模型已发布于 https://anonymous.4open.science/r/Sober-4377。