High-Level Synthesis (HLS) improves IC development productivity by enabling hardware design from C-like languages. However, strict coding constraints and design-specific optimizations limit its widespread adoption. While recent efforts employ large language models (LLMs) to assist HLS design, they often struggle with synthesizability rules and directive semantics. To this end, we introduce ChatHLS, a multi-agent HLS design framework that leverages specialized LLMs for automated debugging and directive tuning. ChatHLS incorporates an adaptive error case expansion mechanism, combined with a reasoning-to-instruction analysis method to accurately diagnose HLS errors. To optimize hardware performance, it enables QoR-aware reasoning to learn the impact of HLS directives on the quality of results (QoR). Experimental results demonstrate that ChatHLS outperforms Gemini-3-pro with a 32.6% relative improvement in debugging, while achieving significant speedups across various HLS kernels and neural network accelerators. These results underscore the potential of ChatHLS for agile hardware development.

翻译：高层次综合（HLS）通过支持类C语言进行硬件设计，提升了集成电路开发效率。然而，严格的编码约束与面向特定设计的优化策略限制了其广泛应用。尽管近期研究尝试利用大型语言模型（LLM）辅助HLS设计，但这些方法在可综合规则理解及指令语义处理方面仍存在不足。为此，我们提出ChatHLS——一种基于多智能体的HLS设计框架，通过专用LLM实现自动化调试与指令调优。该框架融合自适应错误案例扩展机制，并结合推理-指令分析方法，实现HLS错误的精准诊断。在硬件性能优化方面，ChatHLS支持QoR感知的推理学习过程，以掌握HLS指令对结果质量（QoR）的影响。实验结果表明，ChatHLS在调试能力上相对Gemini-3-pro提升32.6%，并在多种HLS内核及神经网络加速器中实现显著加速。这些成果凸显了ChatHLS在敏捷硬件开发中的潜力。