Early, tool-free prediction of post-synthesis timing remains a key obstacle to rapid RTL iteration. We introduce TimingLLM, a two-stage retrieval-augmented LLM pipeline that estimates worst negative slack (WNS) and total negative slack (TNS) directly from Verilog. Stage 1 is a fine-tuned LLM that acts as a compact post-synthesis timing oracle, producing path-level arrivals/required times that are summarized into lightweight structural-timing cues (e.g., bag-of-gates counts, critical-path depth, gate-type patterns). Stage 2 is an LLM-based regressor that predicts WNS/TNS and applies a learned diagonal steering vector at the last transformer block, computed from the k nearest timing-labeled modules in a disjoint retrieval bank. On VerilogEval, TimingLLM attains R_WNS = 0.91 (MAPE 12%) and R_TNS=0.97 (MAPE 16%) while running 1.3-1.6 times faster than prior methods. Training uses a new 60k-module Verilog corpus with synthesis reports, which we will release. After training once, TimingLLM can be adapted to new technology libraries and PVT corners by refitting only a small regression head on 1000 labeled modules per setting, consistently outperforming state-of-the-art baselines.

翻译：早期、免工具的综合后时序预测仍是实现快速RTL迭代的关键障碍。我们提出TimingLLM，这是一种两阶段检索增强的LLM流水线，能够直接从Verilog估计最差负时序余量（WNS）和总负时序余量（TNS）。第一阶段是一个微调后的LLM，充当紧凑的综合后时序“预言机”，生成路径级到达时间/所需时间，这些信息被汇总为轻量级结构时序线索（例如，门级计数袋、关键路径深度、门类型模式）。第二阶段是一个基于LLM的回归器，用于预测WNS/TNS，并在最后一个Transformer块处应用一个学习的对角引导向量，该向量根据不相关检索库中k个最近时序标注模块计算得出。在VerilogEval上，TimingLLM实现了R_WNS=0.91（MAPE 12%）和R_TNS=0.97（MAPE 16%），同时运行速度比先前方法快1.3至1.6倍。训练使用我们即将发布的一个包含综合报告的6万模块新Verilog语料库。一旦完成训练，TimingLLM可通过仅针对每个配置在1000个标注模块上重新拟合一个小的回归头，即可适应新的工艺库和工艺-电压-温度（PVT）角，始终优于最先进的基线方法。