This paper proposes a co-optimization framework that jointly optimizes SRAM architecture and transistor sizing using equivalent circuit models. The framework simplifies inactive SRAM cells into equivalent RC loads and static power models, achieving up to 61.4$\times$ simulation speedup while maintaining high fidelity (read/write delay error $<$0.22%, power error $<$1.68%). A joint search space encompassing architecture parameters and device sizing integrates seven algorithms including SA, PSO, Bayesian Optimization variants, and multi-objective evolutionary algorithms. Based on FreePDK45, ablation experiments confirm complementary gains from architecture selection and transistor sizing. Among all algorithms, MOEA/D achieves the best Figure of Merit (8.2721), yielding 6.2% improvement in SNM, 73.6% reduction in area, and 42.3% reduction in peak power. The framework is publicly available at https://github.com/W1Y1K1/OpenOpt.

翻译：本文提出一种基于等效电路模型协同优化SRAM架构与晶体管尺寸的联合优化框架。该框架将非活动SRAM单元简化为等效RC负载及静态功耗模型，实现高达61.4倍的仿真加速，同时保持高保真度（读写延迟误差<0.22%，功耗误差<1.68%）。联合搜索空间涵盖架构参数与器件尺寸，集成了七种算法，包括SA、PSO、贝叶斯优化变体及多目标进化算法。基于FreePDK45的消融实验证实，架构选择与晶体管尺寸优化可产生互补增益。在所有算法中，MOEA/D取得了最佳品质因数（8.2721），使SNM提升6.2%、面积缩减73.6%、峰值功耗降低42.3%。该框架已开源发布于https://github.com/W1Y1K1/OpenOpt。