The JEDEC committee defines various domain-specific DRAM standards. These standards feature increasingly complex and evolving protocol specifications, which are detailed in timing diagrams and command tables. Understanding these protocols is becoming progressively challenging as new features and complex device hierarchies are difficult to comprehend without an expressive model. While each JEDEC standard features a simplified state machine, this state machine fails to reflect the parallel operation of memory banks. In this paper, we present an evolved modeling approach based on timed Petri nets and Python. This model provides a more accurate representation of DRAM protocols, making them easier to understand and directly executable, which enables the evaluation of interesting metrics and the verification of controller RTL models, DRAM logic and memory simulators.

翻译：JEDEC委员会定义了多种特定领域的DRAM标准。这些标准具有日益复杂且不断演进的协议规范，其细节通过时序图和命令表进行描述。随着新功能和复杂设备层级的引入，若缺乏具有表达力的模型，理解这些协议正变得愈发困难。尽管每个JEDEC标准都配有简化的状态机，但该状态机无法反映存储体的并行操作特性。本文提出一种基于时间Petri网与Python的演进建模方法。该模型能更精确地表征DRAM协议，使其更易于理解且可直接执行，从而支持关键指标评估以及控制器RTL模型、DRAM逻辑与内存模拟器的验证。