As modern analogue/mixed-signal design increasingly relies on optimization-in-the-loop flows, such as AI and LLM-based sizing agents that repeatedly invoke SPICE-efficient, accurate high-performance simulators have become an indispensable foundation for modern integrated circuit (IC) design. However, the computational cost of evaluating nonlinear models, particularly for BSIM models, remains a significant bottleneck. In standard parallelization approaches, devices such as transistors are easily distributed across processors. The subsequent stamping phase, where each device's contributions are added to the shared system matrix, often creates a bottleneck. Because multiple processor cores compete to update the same matrix elements simultaneously, the system is forced to process tasks one at a time to avoid errors. This paper introduces EEspice, an open-source circuit simulation framework whose modular architecture decouples device model evaluation into independently replaceable kernels, enabling a parallel stamping strategy that overcomes this bottleneck. It partitions MOSFET instances into independent color groups, which can be processed in parallel. Our results show that on a 64-core workstation, the proposed approach achieves up to 45x speedup over single-thread performance when conflicts are low. Our analysis also explores how performance depends on circuit topology.

翻译：随着现代模拟/混合信号设计越来越依赖迭代优化流程（如基于AI和LLM的尺寸设计代理需反复调用SPICE），高效、精确的高性能仿真器已成为现代集成电路（IC）设计不可或缺的基础。然而，非线性模型（特别是BSIM模型）的评估计算成本仍是一个重大瓶颈。在标准并行化方法中，晶体管等器件可轻松分配到多个处理器，但后续的填充阶段（每个器件的贡献需加入共享系统矩阵）常形成瓶颈——由于多个处理器核同时争相更新相同矩阵元素，系统被迫串行处理任务以避免错误。本文提出EEspice这一开源电路仿真框架，其模块化架构将器件模型评估解耦为可独立替换的内核，并实现了一种克服该瓶颈的并行填充策略。该方法将MOSFET实例划分为独立颜色组，各组的评估与填充可并行执行。结果表明，在64核工作站上，当冲突较少时，所提方法相比单线程性能可实现高达45倍加速。我们的分析还探讨了电路拓扑结构对性能的影响。