High-Level Synthesis (HLS) improves IC development productivity by enabling hardware design from C-like languages. However, strict coding constraints and design-specific optimizations limit its widespread adoption. While recent efforts employ large language models (LLMs) to assist HLS design, they often struggle with synthesizability rules and directive semantics. To this end, we introduce ChatHLS, a multi-agent HLS design framework that leverages specialized LLMs for automated debugging and directive tuning. ChatHLS incorporates an adaptive error case expansion mechanism, combined with a reasoning-to-instruction analysis method to accurately diagnose HLS errors. To optimize hardware performance, it enables QoR-aware reasoning to learn the impact of HLS directives on the quality of results (QoR). Experimental results demonstrate that ChatHLS outperforms Gemini-3-pro with a 32.6% relative improvement in debugging, while achieving significant speedups across various HLS kernels and neural network accelerators. These results underscore the potential of ChatHLS for agile hardware development.

翻译：高层次综合（HLS）通过支持从类C语言进行硬件设计，提升了集成电路开发效率。然而，严格的编码约束与特定设计的优化限制了其广泛应用。尽管近期研究尝试利用大语言模型（LLM）辅助HLS设计，但这些方法常难以处理可综合规则与指令语义。为此，我们提出ChatHLS——一种基于多智能体的HLS设计框架，利用专用LLM实现自动化调试与指令调优。ChatHLS集成了自适应错误案例扩展机制，并结合推理到指令的分析方法，可精确诊断HLS错误。为优化硬件性能，该框架支持QoR感知推理，以学习HLS指令对结果质量（QoR）的影响。实验结果表明，ChatHLS在调试任务中相较Gemini-3-pro实现32.6%的相对性能提升，并在多种HLS内核与神经网络加速器上取得显著加速效果。这些结果凸显了ChatHLS在敏捷硬件开发中的潜力。